1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device for preventing against electrostatic discharge using a profiled well process.
2. Description of the Related Art
Electrostatic discharge (ESD) is one among factors determining reliability of a semiconductor chip. Such ESD is generated when handling the semiconductor chip and utilizing it in various applications and causes damage to the semiconductor chip. To protect the semiconductor chip from ESD damage, a protection circuit against ESD is provided along with the semiconductor chip.
FIG. 1 shows a conventional protection circuit against ESD. Referring to FIG. 1, a protection circuit against ESD 200 is inserted between an input pad 100 and an inside circuit 300. The protection circuit against ESD 200 includes a field transistor FD, a NMOS transistor NM connected to the field transistor FD in parallel, and a resistor R inserted between the field transistor FD and the NMOS transistor NM. The gate and drain of the field transistor FD are connected to the input pad 100, respectively and its source is connected to a power source VSS. The field transistor FD has a thick field oxide layer acting as a gate oxide layer. The drain of the field transistor FD is also an input portion of the protection circuit against ESD 200. The resistor R drops a voltage of the input pad 100 between the input pad 100 and the NMOS transistor NM. The resistor R is connected to the drains of the field transistor FD and of the NMOS transistor NM. The gate and source of the NMOS transistor NM are connected to the power source VSS.
In case ESD of a high voltage is generated at the input pad 100, the field transistor FD is turned on and it is prevented that the high voltage is applied to the inside circuit 300. On the other hand, in case ESD of a high voltage less than the power source VSS is generated at the input pad 100, the NMOS transistor NM is turned on and it is prevented that the high voltage is applied to the inside circuit 300.
FIG. 2 shows a cross sectional view of the field transistor FD of the protection circuit against ESD 200 in FIG. 1. Referring to FIG. 2, first, second, and third field oxide layers 21a, 21b, and 21c are formed on the semiconductor substrate 20 by a LOCOS (LOCal Oxidation of Silicon) technique. The second field oxide layer 21b between the first and third field oxide layers 21a and 21c, is a gate oxide layer. A N well for ESD 22 is formed in the substrate 20 on one side of the second field oxide layer 21b. A p well 23 is formed in the substrate 20 to join to the N well for ESD 22. A gate 24 is formed on the second field oxide layer 21b. First and second N.sup.+ junction regions 25a and 25b are formed in the N well for ESD 22 and the P well 23 on both sides of the gate 24, respectively. Here, the first N.sup.+ junction region 25a is a source and the second N.sup.+ junction region 25b is a drain which will be connected to the input pad 100 (refer to FIG. 1).
As above described, by the N well for ESD 22 under the second N.sup.+ junction region 25b, a leakage current due to a junction spiking caused by the ESD, is prevented and a breakdown voltage increases at a PN junction. As a result, the semiconductor chip is protected effectively from ESD generated at the input pad 100.
The N well for ESD 22 and the P well 23 are formed by a profiled well process that N type and P type impurity ions are implanted into the substrate 20 by a step-by-step ion implanting according to the depth of the substrate 20 and then an annealing is performed to diffuse the N type and P type impurity ions. At this time, the annealing is performed at a low temperature for a short time by the step-by-step ion implanting of the impurity ions, thereby decreasing a process time.
On the other hand, owing to a step-by-step distribution of impurity ions according to the depth of the substrate, the impurity concentration profile of the well is nonuniform. This concentration profile is further nonuniform at junction faces between the P well 23 and the N well for ESD 22 and between the second N.sup.+ junction region 25b and the N well for ESD 22, thereby generating a valley D to the N well for ESD 22, as shown in FIG. 2. The depth of The valley is further deep due to a counter doping caused by forming the P well 23. FIG. 3 shows impurity concentration distribution profile according to the depth of the substrate. As shown in FIG. 3, the profile is nonuniform at a depth X1 of the junction face of the second N.sup.+ junction region 25b and the N well for ESD 22 and at a depth X2 of the valley.
When operating the field transistor, an electric field concentrates at the valley, so that breakdown generates at the valley, firstly. As a result, current is crowded locally, so that the device is heated, thereby deteriorating the device. Furthermore, a junction spiking is generated at the second N.sup.+ junction region 25b due to the concentration of the electric field. Finally, the semiconductor chip is not effectively protected from ESD generated at the input pad 100, so that it is damaged.